Select the correct statement(s) regarding CMOS implementation of NOT gates.

CMOS NOT Gate Fundamentals

A CMOS NOT gate, also known as a CMOS inverter, is a fundamental building block in digital electronics. It consists of a pMOS transistor and an nMOS transistor connected in series between the power supply (V${}_{DD}$) and ground, with the input connected to both gates and the output taken from the common drain connection. Understanding its operation, power consumption, noise characteristics, and switching speed is crucial for digital circuit design.

CMOS Inverter Statement Analysis

Let's carefully evaluate each provided statement regarding the CMOS implementation of NOT gates.

**1. Noise Margin High (NM${}_H$) and Noise Margin Low (NM${}_L$)

The statement claims that Noise Margin High (NM${}_H$) is always equal to the Noise Margin Low (NM${}_L$), irrespective of the sizing of transistors.

- Noise Margins:** NM${}_H$ and NM${}_L$ are measures of a circuit's ability to tolerate noise on its input without causing an incorrect output. They are defined as: ${\text{NM}}_{\text{H}}={\text{V}}_{\text{OH}}-{\text{V}}_{\text{IH}}$ ${\text{NM}}_{\text{L}}={\text{V}}_{\text{IL}}-{\text{V}}_{\text{OL}}$ Where V${}_{OH}$ is output high voltage, V${}_{IH}$ is input high voltage threshold, V${}_{IL}$ is input low voltage threshold, and V${}_{OL}$ is output low voltage.
- Transistor Sizing (W/L): The threshold voltages V${}_{IH}$ and V${}_{IL}$, and thus the noise margins, are directly dependent on the dimensions (width W and length L) of the nMOS and pMOS transistors. Specifically, the ratio of the transconductance parameters ($k_n^{\prime }\frac{W_n}{L_n}$ and $k_p^{\prime }\frac{W_p}{L_p}$) of the nMOS and pMOS transistors determines the voltage transfer characteristics (VTC) of the inverter.
- Symmetry: For an ideal symmetric inverter where NM${}_H$ = NM${}_L$, the relationship between the transistor sizes and mobilities is approximately given by $\frac{W_p}{L_p}\approx \frac{{\mu }_n}{{\mu }_p}\frac{W_n}{L_n}$. Since the electron mobility (${\mu }_n$) is typically 2 to 3 times greater than the hole mobility (${\mu }_p$), this implies that for equal noise margins, the pMOS transistor must be wider than the nMOS transistor ($W_p>W_n$).
- Conclusion: Since noise margins are influenced by transistor sizing, they are not always equal irrespective of sizing. Therefore, this statement is incorrect.

2. Dynamic Power Consumption

The statement posits that Dynamic power consumption during switching is zero.

- Dynamic Power Components: Dynamic power is consumed in CMOS circuits primarily during switching transitions. It has two main components: 1. Capacitive Power: This is due to the charging and discharging of the load capacitance (C${}_L$) at the output of the gate. Every time the output switches from low to high or high to low, the load capacitance is charged or discharged, consuming energy. The formula for capacitive dynamic power is $P_{\text{dynamic, cap}}=C_L{V}_{DD}^{2}f$, where $f$ is the switching frequency. 2. Short-Circuit Power: This occurs when both the nMOS and pMOS transistors are simultaneously conducting for a brief period during the input transition from logic low to logic high or vice versa. This creates a direct path (short circuit) between V${}_{DD}$ and ground, leading to current flow and power dissipation.
- Conclusion: Since there is always a load capacitance that needs to be charged/discharged and there are short-circuit currents during transitions, dynamic power consumption is never zero in a real CMOS circuit. Therefore, this statement is incorrect.

3. nMOSFET Operation Regime for High Input

The statement suggests that For a logical high input under steady state, the nMOSFET is in the linear regime of operation.

- Steady State with High Input: When the input to a CMOS NOT gate (inverter) is a logical high (Vᵢₙ = V${}_{DD}$), the circuit reaches a steady state.
- nMOSFET State Analysis: 1. The gate-source voltage for the nMOSFET is $V_{GS}=V_{in}-0=V_{DD}$. As $V_{DD}>V_{Tn}$ (threshold voltage of nMOS), the nMOSFET is turned ON. 2. The nMOSFET pulls the output voltage (Vₒᵤₜ) down towards ground. In steady state, the output approaches 0 V (V${}_{OL}$ ≈ 0 V). 3. The drain-source voltage for the nMOSFET is $V_{DS}=V_{out}-0\approx 0\text{ V}$.
- Operating Regime Conditions: 1. An nMOSFET is in the linear (triode or ohmic) region when $V_{DS}<(V_{GS}-V_{Tn})$. 2. An nMOSFET is in the saturation region when $V_{DS}\ge (V_{GS}-V_{Tn})$.
- Applying Conditions: Given $V_{GS}=V_{DD}$ and $V_{DS}\approx 0\text{ V}$. Since $V_{DD}>V_{Tn}$, the term $(V_{GS}-V_{Tn})=(V_{DD}-V_{Tn})$ is a positive value. It is clear that $0\text{ V}<(V_{DD}-V_{Tn})$.
- Conclusion: Because $V_{DS}<(V_{GS}-V_{Tn})$, the nMOSFET operates in the linear (triode) region. This statement is correct.
- pMOSFET State (for completeness): When Vᵢₙ = V${}_{DD}$, for the pMOSFET, $V_{GS}=V_{in}-V_{DD}=V_{DD}-V_{DD}=0\text{ V}$. Since $|V_{GS}|<|V_{Tp}|$ (threshold voltage of pMOS), the pMOSFET is in the cut-off region (OFF).

4. Electron Mobility and Switching Speed

The statement asserts that Mobility of electrons never influences the switching speed of the NOT gate.

- Switching Speed Definition: The switching speed of a CMOS gate refers to how quickly the output can transition from one logic state to another, typically measured by propagation delays (t${}_{PLH}$ and t${}_{PHL}$).
- Influence of Carrier Mobility: 1. The drain current (I${}_D$) of a MOSFET is directly proportional to the carrier mobility (${\mu }_n$ for electrons in nMOS and ${\mu }_p$ for holes in pMOS). For example, in saturation, $I_D\propto \mu \left(\frac{W}{L}\right)(V_{GS}-V_T{)}^2$. 2. This current determines how fast the load capacitance at the output can be charged or discharged. Higher current leads to faster charging/discharging. 3. Specifically, the pull-down time (t${}_{PHL}$) when the nMOSFET pulls the output low is strongly influenced by electron mobility (${\mu }_n$). 4. Similarly, the pull-up time (t${}_{PLH}$) when the pMOSFET pulls the output high is influenced by hole mobility (${\mu }_p$).
- Conclusion: Since transistor currents are directly dependent on carrier mobility, and these currents dictate the charging/discharging speed of the output capacitance, the mobility of electrons (and holes) significantly influences the switching speed of the NOT gate. Therefore, this statement is incorrect.

Correct Statement Summary

Based on the detailed analysis of each option, the correct statement regarding CMOS implementation of NOT gates is that for a logical high input under steady state, the nMOSFET is in the linear regime of operation.