GATE EC 2015 Question Paper (31-Jan-2015) (Shift 1)

The Boolean expression $\mathrm{F}\left(\mathrm{x},\mathrm{y},\mathrm{z}\right)=\bar{\mathrm{x}}\mathrm{y}\bar{\mathrm{z}}+\mathrm{x}\bar{\mathrm{y}}\bar{\mathrm{z}}+\mathrm{x}\mathrm{y}\bar{\mathrm{z}}+\mathrm{x}\mathrm{y}\mathrm{z}$ is converted into the canonical product of sum (POS) form is

All the logic gates shown in the figure have a propagation delay of 20ns. Let $\mathrm{A}=\mathrm{C}=0$ and $\mathrm{B}=1$ until time $\mathrm{t}=0$. At $\mathrm{t}=0$, all the inputs flip (i.e, $\mathrm{A}=\mathrm{C}=1$ and $\mathrm{B}=0$) and remain in that state. For $\mathrm{t}>0$, output $\mathrm{Z}=1$ for a duration (in ns) of

A 3 - input majority gate is defined by the logic function $\mathrm{M}\left(\mathrm{a},\mathrm{b},\mathrm{c}\right)=\mathrm{ab}+\mathrm{bc}+\mathrm{ac}$ . Which one of the following gate is represented by the function $\mathrm{M}\left(\overline{\mathrm{M}\left(\mathrm{a},\mathrm{b},\mathrm{c}\right)},\mathrm{M}\left(\mathrm{a},\mathrm{b},\overline{\mathrm{c}}\right),\mathrm{c}\right)?$

For the NMOSFET in the circuit shown, the threshold voltage is Vₜₕ, where Vₜₕ> 0. The source voltage V${}_{SS}$ is varied from 0 to V${}_{DD}$. Neglecting the channel length modulation, the drain current I${}_D$ as a function of V${}_{SS}$ is represented by

In the circuit shown, assume that the Op-Amp is ideal. The bridge output voltage V₀ (in mV)

For, δ = 0.05 is _______________________.