GATE EC 2016 Question Paper (31-Jan-2016) (Shift 1)

An opamp has a finite open-loop voltage gain of 100. Its input offset voltage Vᵢₒₛ (= +5mV) is modeled as shown in the circuit below. The amplifier is ideal in all other respects. V${}_{input}$ is 25 mV.



The output voltage (in millivolts) is _________.

An 8 Kbyte ROM with an active low Chip Select input$\left(\overline{\mathrm{CS}}\right)$ is to be used in an 8085 microprocessor-based system. The ROM should occupy the address range 1000H to 2FFFH. The address lines are designated as 𝐴₁₅ to 𝐴₀, where 𝐴₁₅ is the most significant address bit. Which one of the following logic expressions will generate the correct $\overline{\mathrm{CS}}$ signal for this ROM?

In an N bit flash ADC, the analog voltage is fed simultaneously to 2${}^{\text{N}}$ − 1 comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source Vᵢₙ (whose output is being converted to digital format) has a source resistance of 75 Ω as shown in the circuit diagram below and the input capacitance of each comparator is 8 pF.

The input must settle to an accuracy of 1/2 LSB even for a full-scale input change for proper conversion. Assume that the time taken by the thermometer to the binary encoder is negligible.



If the flash ADC has 8-bit resolution, which one of the following alternatives is closest to the maximum sampling rate?

The state transition diagram for a finite state machine with states A, B and C, and binary inputs X,

Y and Z, is shown in the figure.



Which one of the following statements is correct?

In the feedback system shown below $\mathrm{G}(\mathrm{s})=\frac{1}{\left({\mathrm{s}}^2+2\mathrm{s}\right)}$

The step response of the closed-loop system should have a minimum settling time and have no overshoot.



The required value of gain 𝑘 to achieve this is ________