GATE EC 2016 Question Paper (31-Jan-2016) (Shift 1)

Transistor geometries in a CMOS inverter have been adjusted to meet the requirement for worst-case charge and discharge times for driving a load capacitor C. This design is to be converted to that of a NOR circuit in the same technology, so that its worst-case charge and discharge times while driving the same capacitor are similar. The channel lengths of all transistors are to be kept unchanged. Which one of the following statements is correct?

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R = 10 kΩ, and the supply voltage is 5 V. The D flip-flops D1, D2, D3, D4, and D5 are initialized with logic values 0, 1, 0, 1, and 0 respectively. The clock has a 30% duty cycle.



The average power dissipated (in mW) in the resistor R is ________

A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while Cᵢₙ is the input carry and Cₒᵤₜ is the output carry. A and B are to be used as the select bits with A being the more significant select bit.

The response of the system $\mathrm{G}\left(\mathrm{s}\right)=\frac{\mathrm{s}-2}{\left(\mathrm{s}+1\right)\left(\mathrm{s}+3\right)}$ to the unit step input $\mathrm{u}(\mathrm{t})$ is $\mathrm{y}(\mathrm{t})$.

The value of $\frac{\mathrm{dy}}{\mathrm{dt}}$ at $\mathrm{t}=0^{+}$ is _________

The number and direction of encirclements around the point $-1+j0$ in the complex plane by the Nyquist plot of $\mathrm{G}\left(\mathrm{s}\right)=\frac{1-\mathrm{s}}{4+2\mathrm{s}}$ is