GATE EC 2016 Question Paper (31-Jan-2016) (Shift 2)

In the circuit shown in the figure, the channel length modulation of all transistors is non-zero ($\lambda \ne 0$). Also, all transistors operate in saturation and have negligible body effect. The ac small signal voltage gain $(V_o/V_{in})$ of the circuit is

In the circuit shown in the figure, transistor M1 is in saturation and has transconductance $g_m=0.01\text{siemens}$. Ignoring internal parasitic capacitances and assuming the channel length modulation $\lambda$ to be zero, the small signal input pole frequency (in kHz) is ___________

Following is the K-map of a Boolean function of five variables P, Q, R, S and X. The minimum sum-of-product (SOP) expression for the function is

For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2\text{ns}$, $1.5\text{ns}$ and $1\text{ns}$, respectively. If all the inputs P, Q, R, S and T are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is ____________

For the circuit shown in the figure, the delay of the bubbled NAND gate is 2 ns and that of the counter is assumed to be zero.



If the clock (Clk) frequency is 1 GHz, then the counter behaves as a