GATE EC 2017 Question Paper (05-Feb-2017) (Shift 1)

The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to execute an instruction is 1.4 μs, then the number of T-states needed for executing the instruction is

Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output of the latch, in percentage is ________.

The open loop transfer function $G\left(s\right)=\frac{\left(s+1\right)}{s^p\left(s+2\right)\left(s+3\right)}$

Where p is an integer, is conducted in unity feedback configuration as shown in the figure.



Given that the steady state error is zero for unit step input and is 6 for unit ramp input, the value of the parameter p is______.

Consider a stable system with the transfer function $\left(s\right)=\frac{s^p+b_1{s}^{p-1}+\dots +b_p}{s^q+a_1{s}^{q-1}+\dots +a_q}$

Where b₁, …, bₚ and a₁, …, a${}_q$ are real-valued constants. The slope of the Bode log magnitude curve of G(s) converges to – 60 dB/decade as ω → ∞. A possible pair of values for p and q is

Which of the following can be the pole-zero configuration of a phase-lag controller (lag compensator)?