GATE EE 2015 Question Paper (07-Feb-2015) (Shift 1)

The circuit shown in meant to supply a resistive load R${}_L$ from two separate DC voltage sources. The switches S₁ and S₂ are controlled so that only one of them is ON at any instant S₁ is turned on for 0.2 ms ad S₂ is turned on for 0.3 ms in a 0.5 ms switching cycle time period. Assuming continuous conduction of the inductor current and negligible ripple on the capacitor voltage, the output voltage V${}_O$ (in volt) across R${}_L$ is –

A self-commutating switch SW, operated at duty cycle $\delta$ is used to control the load voltage as shown in the figure.



Under steady state operating conditions, the average voltage across the inductor and the capacitor respectively, are

The single-phase full-bridge voltage source inverter (VSI), shown in figure, has an output frequency of $50Hz$. It uses unipolar pulse width modulation with switching frequency of $50kHz$ modulation index of 0.7. For $V_{in}=100V$ DC, $L=9.55mH,C=63.66\mu F$, and $R=5\Omega$, the amplitude of the fundamental component in the output voltage $V_0$ (in volt) under steady-state is ___________.

A 3-phase $50Hz$ square wave (6-step) VSI feeds a 3-phase, 4 pole induction motor. The VSI line voltage has a dominant $5^{th}$ harmonic component. If the operating slip of the motor with respect to fundamental component voltage is 0.04, the slip of the motor with respect to $5^{th}$ harmonic component of voltage is ______.

Consider a discrete time signal given by

$x\left[n\right]={\left(-0.25\right)}^{n}u\left[n\right]+{\left(0.5\right)}^{n}u\left[-n-1\right]$

The region of convergence of its Z – transform would be