GATE EE 2016 Question Paper (06-Feb-2016) (Shift 2)

The current state Q${}_A$ Q${}_B$ of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is

A 2-bit flash Analog to Digital Converter (ADC) is given below. The input is $0\le V_{IN}\le 3$ Volts. The expression for the LSB of the output $B_0$ as a Boolean function of $X_2,X_1,$ and $X_0$ is

Two electric charges q and -2q are placed at (0,0) and (6,0) on the x-y plane. The equation of the zero equipotential curve in the x-yplane is

In the circuit shown, switch $S_2$ has been closed for a long time. At time $t=0$ switch $S_1$ is closed. At $t=0^{+}$, the rate of change of current through the inductor, in amperes per second, is _____.

A three-phase cable is supplying $800kW$ and $600kVAr$ to an inductive load. It is intended to supply an additional resistive load of $100kW$ through the same cable without increasing the heat dissipation in the cable, by providing a three-phase bank of capacitors connected in star across the load. Given the line voltage is $3.3kV,50Hz$, the capacitance per phase of the bank, expressed in microfarads, is ________.