GATE EE 2017 Question Paper (11-Feb-2017) (Shift 1)

The output expression for the Karnaugh map shown below is:

The logical gate implemented using the circuit shown below where, V₁ and V₂ are inputs (with 0 V as digital 0 and 5 V as digital 1) and V${}_{OUT}$ is the output, is

The input voltage V${}_{DC}$ of the buck-boost converter shown below varies from 32 V to 72 V. Assume that all components are ideal, inductor current is continuous, and output voltage is ripple free. The range of duty ratio D of the converter for which the magnitude of the steady-state output voltage remains constant at 48 V is

A load is supplied by a 230 V, 50 Hz source. The active power P and the reactive power Q consumed by the load are such that 1 kW ≤ P ≤ 2 kW and 1 kVAR ≤ Q ≤ 2 kVAR. A capacitor connected across the load for power factor correction generates 1 kVAR reactive power. The worst case power factor after power factor connection is

The bus admittance matrix for a power system network is

≤ft[ {*20c - j39.9&j20&j20\\ j20& - j39.9&j20\\ j20&j20& - j39.9 } ]pu

There is a transmission line, connected between buses 1 and 3, which is represented by the circuit shown in figure.



If this transmission line is removed from service, what is the modified bus admittance matrix?