GATE IN 2015 Question Paper (01-Feb-2015) (Shift 2)

A load resistor R${}_L$ is connected to a battery of voltage E with internal resistance Rᵢ through a resistance R${}_S$ as shown in the figure. For fixed values of R${}_L$ and Rᵢ, the value of R${}_S$ (≥ 0) for maximum power transfer to R${}_L$ is

Consider the logic circuit with input signal TEST shown in the figure. All gates in the figure shown have identical non-zero delay. The signal TEST which was at logic LOW is switched to logic HIGH and maintained at logic HIGH. The output

The logic evaluated by the circuit at the output is

In the circuit shown, the switch is momentarily closed and then opened. Assuming the logic gates to have equal non-zero delay, at steady state, the logic states of X and Y are

The highest frequency present in the signal x(t) is f${}_{max}$. The highest frequency present in the signal y(t) = x²(t) is