GATE IN 2016 Question Paper (31-Jan-2016) (Shift 2)

A 1 Kbyte memory module has to be interfaced with an 8-bit microprocessor that has 16 address lines. The address lines A₀ to A₉ of the processor are connected to the corresponding address lines fo the memory module. The active low chip select $\overline{CS}$ of the memory module is connected to the y₅ output of a 3 to 8 decoder with active low outputs. S₀, S₁, and S₂ are the input lines to the decoder, with S₂ as the MSB. The decoder has one active low ${\overline{EN}}_1$ and one active high EN₂ enable lines as shown below. The address range(s) that gets mapped onto this memory module is (are)

A coil is tested with a series type Q-meter. Resonance at a particular frequency is obtained with a capacitance of 110 pF. When the frequency is doubled, the capacitance required for resonance is 20 pF. The distributed capacitance of the coil in pico farad is ______.

The comparators (output = ‘1’, when input ≥ 0 and output = ‘0’, when input < 0), exclusive-OR gate and the unity gain low-pass filter given in the circuit are ideal. The logic output voltages of the exclusive-OR gate are 0 V and 5 V. The cutoff frequency of the low-pass filter is 0.1 Hz. For V₁ = 1 sin (3000t + 36${}^o$) V and V₂ = 1 sin (3000t) V, the value of V${}_O$ in volt is ______.

A 200 mV full scale dual-slope 3 ½ digit DMM has a reference voltage of 100 mV and a first integration time of 100 ms. For an input of [100 + 10 Cos (100πt)] mV, the conversion time (without taking the auto-zero phase time into consideration) in millisecond is______.

In the circuit below, the opamp is ideal and the sensor is an RTD whose resistance R${}_{\theta }$ = 1000 (1 + 0.004θ) Ω, where θ is temperature in °C. The output sensitivity in mv/°C is ________.