GATE IN 2024 Question Paper (04-Feb-2024) (Shift 2)

In the figure shown, both the opamps $A_1$ and $A_2$ are ideal, except that the opamp $A_1$ has an offset voltage ($V_{os}$) of $1mV$. For $V_{in}=0V$, the values of the output voltages $V_{out1}$ and $V_{out2}$, respectively, are

In the figure shown, the positive edge triggered D flip-flops are initially reset to $Q=0$. The logic gates and the multiplexers have no propagation delay. After reset, a train of clock pulses (CLK) are applied. The logic-states of the inputs DIN, S and the clock pulses are also shown in the figure. Assuming no timing violations, the sequence of output Y from the $3^{rd}$ clock to the $5^{th}$ clock, $Y_3{Y}_4{Y}_5$ is

In the figure shown, $R=1k\Omega$ and $C=0.1\mu F$. For a dc gain of $-10$, the $3dB$ cut-off frequency (rounded off to one decimal place) is
Assume the opamp is ideal.

Consider the feedback control system shown in the figure. The steady-state error $e_{ss}={\lim }_{t\to \infty }(r(t)\text{–}y(t))$ due to unit step reference $r(t)$ is

The transfer function of a system is
$G(s)=\frac{{\omega }_n^2}{s^2+2\xi {\omega }_{n}s+{\omega }_n^2}$
Choose the range of $\xi$ and ${\omega }_n$ (in rad/s) from the following options such that the poles lie on the shaded region of the s-plane as shown in the figure.