PYQs Based Test - 06 : Digital Electronics

In the circuit shown, the switch is momentarily closed and then opened. Assuming the logic gates to have equal non-zero delay, at steady state, the logic states of X and Y are

Two T-flip flops are interconnected as shown in the figure. The present state of the flip flops are: A = 1, B = 1. The input x is given as 1, 0, 1 in the next three clock cycles. The decimal equivalent of (ABy)₂ with A being the MSB and y being the L.S.B. after the 3${}^{rd}$ clock cycle is _______

For the circuit shown in the figure, the rising edge triggered D-flip flop with asynchronous reset has a clock frequency of 1 Hz. The NMOS transistor has an ON resistance of 1000Ω and an OFF resistance of infinity. The nature of the output waveform is

A portion of an assembly language program written for an 8-bit microprocessor is given below along with explanations. The code is intended to introduce a software time delay. The processor is driven by a 5 MHz clock. The time delay (in μs) introduced by the program is _______.

MVI B, 64H ; Move immediate the given byte into register B. Takes 7 clock periods.

LOOP: DCR B; Decrement register B. Affects Flags. Takes 4 clock periods.

JNZ LOOP; Jump to address with Label LOOP if zero flag is not set. Takes 10 clock periods when jump is performed and 7 clock periods when jump is not performed.

A 16-bit microprocessor has twenty address lines (A₀ to A₁₉) and 16 data lines. The higher eight significant lines of the data bus of the processor are tied to the 8-data lines of a 16 Kbyte memory that can store one byte in each of its 16K address locations. The memory chip should map onto contiguous memory locations and occupy only 16 Kbyte of memory space. Which of the following statement(s) is/are correct with respect to the above design?