PYQs Based test 20: Digital Electronics

The current state Q${}_A$ Q${}_B$ of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is

In the circuit shown below, X and Y are digital inputs, and Z is a digital output. The equivalent circuit is a

In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is Q₁Q₀ = 00. The state (Q₁Q₀) after the 333${}^{rd}$ clock pulse is

The output expression for the Karnaugh map shown below is

An 8-bit, unipolar successive approximation Register type ADC is used to convert 3.5 V to digital equivalent output. The reference voltage is +5V. The output of the ADC at the end of third clock pulse after start of conversion, is