GATE EC 2015 Question Paper (01-Feb-2015) (Shift 1)

A three-bit pseudo-random number generator is shown. Initially, the value of output Y = Y₂ Y₁ Y₀ is set to 111. The value of output Y after three clock cycles is:

A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown:



Which one of the following statements is TRUE?

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing

In the circuit shown, assume that the op-amp is ideal. If the gain (vₒ/vᵢₙ) is –12, the value of R (in kΩ) is _____.

In the circuit shown, both the enhancement mode NMOS transistors have the following characteristics: kₙ = μₙCₒₓ (W/L) = 1 mA/V²; V${}_{TN}$ = 1 V. Assume that the channel length modulation parameter λ is zero and body is shorted to the source. The minimum supply voltage V${}_{DD}$ (in volts) needed to ensure that transistor M₁ operates in saturation mode of operation is ________.