GATE EC 2015 Question Paper (01-Feb-2015) (Shift 1)

In the circuit shown in the figure, the BJT has a current gain (β) of 50. For an emitter-base voltage V${}_{EB}$ = 600 mV, the emitter-collector voltage V${}_{EC}$ (in Volts) is _____Volts.

In the circuit shown using an ideal op-amp, the 3-dB cut-off frequency (in Hz) is ______.

In the circuit shown, assume that diodes D₁ and D₂ are ideal. In the steady-state condition, the average voltage V${}_{ab}$ (in Volts) across the 0.5 μF capacitor is ______.

The circuit as shown consists of J-K flip-flops, each with an active low asynchronous reset $\left(\overline{R_d}input\right).$ The counter corresponding to this circuit is:

In the circuit shown, diodes D₁, D₂ and D₃ are ideal, and the inputs E₁, E₂ and E₃ are “0 V” for logic ‘0’ and “10 V” for logic ‘1’. What logic gate does the circuit represent?