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GATE EC 2016 Question Paper (30-Jan-2016) (Shift 1)

Medium 65 Questions 180 min 100 marks

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Question No: 26Difficulty: mediumMarks: 1mcq

The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-by-𝑁 counter (comprising \div 2 ,\div 4, \div 8, \div 16 outputs) is sketched below. The synthesizer is excited with a 5 kHz signal (Input 1). The free-running frequency of the PLL is set to 20 kHz. Assume that the commutator switch makes contacts repeatedly in the order 1-2-3-4. The corresponding frequencies synthesized are:

Question No: 27Difficulty: mediumMarks: 1mcq

The output of the combinational circuit given below is

Question No: 28Difficulty: mediumMarks: 1mcq

What is the voltage Vₒᵤₜ in the following circuit?

Question No: 29Difficulty: mediumMarks: 1mcq

Match the inferences X, Y, and Z, about a system, to the corresponding properties of the elements of first column in Routh’s Table of the system characteristic equation. X: The system is stable \dots Y: The system is unstable \dots Z: The test breaks down \dots P: \dots when all elements are positive Q: \dots when any one element is zero R: \dots when there is a change in sign of coefficients

Question No: 30Difficulty: mediumMarks: 1mcq

A closed-loop control system is stable if the Nyquist plot of the corresponding open-loop transfer function

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