GATE EE 2017 Question Paper (11-Feb-2017) (Shift 2)

Consider the following system described by the following state space representation.

≤ft[ {*20c x_1 ≤ft( t )\\ x_2 ≤ft( t ) } ] = ≤ft[ {*20c 0&1\\ 0& - 2 } ]≤ft[ {*20c x_1≤ft( t )\\ x_2≤ft( t ) } ] + ≤ft[ {*20c 0\\ 1 } ]u≤ft( t )

y≤ft( t ) = ≤ft[ {*20c 1&0 } ]≤ft[ {*20c x_1≤ft( t )\\ x_2≤ft( t ) } ]

If u(t) is a unit step input and ≤ft[ {*20c x_1≤ft( 0 )\\ x_2≤ft( 0 ) } ] = ≤ft[ {*20c 1\\ 0 } ], the value of output y(t) at t = 1 sec (round off to three decimal places) is ________

A 10 ½ digit timer counter possesses a base clock of frequency 100 MHz. When measuring a particular input, the reading obtained is the same in: (i) Frequency mode of operation with a gating time of one second and (ii) Period mode of operation (in the × 10 ns scale). The frequency of the unknown input (reading obtained) in Hz is _____________.

In the circuit shown in the figure, the diode used is ideal. The input power factor is __________. (Give the answer up to two-decimal places.)

For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions $Q_A{Q}_B{Q}_C=Q_A^{\prime }{Q}_B^{\prime }{Q}_C^{\prime }=100$.



The minimum number of clock cycles after which the output Z would again become zero is _______.

In the circuit shown all elements are ideal and the switch S is operated at 10 kHz and 60% duty ratio. The capacitor is large enough so that the ripple across it is negligible and at steady state acquires a voltage as shown. The peak current in amperes drawn from the 50 V DC source is _________. (Give the answer up to one decimal place.)