PYQs Based Test - 06 : Digital Electronics

The circuit shown in the figure below uses ideal positive edge-triggered synchronous J-K flip flops with outputs X and Y. If the initial state of the output is X = 0 and Y = 0 just before the arrival of the first clock pulse, the state of the output just before the arrival of the second clock pulse is

A $10\frac{1}{2}$ digit Counter-timer is set in the ‘frequency mode’ of operation (with Tₛ = 1 s). For a specific input, the reading obtained is 1000. Without disconnecting this input, the Counter-timer is changed to operate in the ‘Period mode’ and the range selected is microseconds (μs, with fₛ= 1 MHz). The counter will then display

The address lines A₉ ... A₂ of a 10 bit, 1.023 V full-scale digital to analog converter (DAC) is connected to the data lines D₇ to D₀ of an 8-bit microprocessor, with A₁ and A₀ of the DAC grounded. Now, D₇ ... D₀ is changed from 1010 1010 to 1010 1011. The corresponding change in the output of the DAC (in mV, rounded off to one decimal place) is

A 200 mV full-scale dual-slope analog to digital converter (DS-ADC) has a reference voltage of 100 mV. The first integration time is set as 100 ms. The DS-ADC is operated in the continuous conversion mode. The conversion time of the DS-ADC for an input voltage of 123.4 mV (in ms, rounded off to one decimal place) is

The two inputs A and B are connected to a NOR based R-S latch, via two AND gates as shown in the figure. If A = 1 and B = 0, the output QQ̅ is