PYQs Based test 21: Digital Electronics

The figure below shows a multiplexer where S₁ and S₀ are the select lines, I₀ to I₃ are the input data lines, EN is the enable line, and F(P, Q, R) is the output. F is

A 200 mV full-scale dual-slope analog to digital converter (DS-ADC) has a reference voltage of 100 mV. The first integration time is set as 100 ms. The DS-ADC is operated in the continuous conversion mode. The conversion time of the DS-ADC for an input voltage of 123.4 mV (in ms, rounded off to one decimal place) is

Consider the logic circuit with input signal TEST shown in the figure. All gates in the figure shown have identical non-zero delay. The signal TEST which was at logic LOW is switched to logic HIGH and maintained at logic HIGH. The output

The two inputs A and B are connected to a NOR based R-S latch, via two AND gates as shown in the figure. If A = 1 and B = 0, the output QQ̅ is

X = X₁X₀ and Y = Y₁Y₀ are 2-bit binary numbers. The Boolean function S that satisfies the condition “If X > Y, then S = 1”, in its minimized form, is