PYQs Based test 21: Digital Electronics

Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output of the latch, in percentage is ________.

For a 4-bit Flash type Analog to Digital Convertor (ADC) with full scale input voltage range “V”, which of the following statement(s) is/are true ?

The propagation delays of the XOR gate, AND gate, and multiplexer (MUX) in the circuit shown in the figure are 4 ns, 2 ns, and 1 ns, respectively.



If all the inputs P, Q, R, S, and T are applied simultaneously and held constant the maximum propagation delay of the circuit is

If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtractor?

In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12 kHz.The frequency of the signal at Q₂ is ____ kHz.