PYQs Based Test - 07 : Digital Electronics

In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12 kHz.The frequency of the signal at Q₂ is ____ kHz.

A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are Q${}_A$ Q${}_B$ = 00,01,10, and 11.



Assume that X${}_{IN}$ is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state Q${}_A$ Q${}_B$ = 00 and clocked, after a few clock cycles, it starts cycling through

In the circuit shown below, a positive edge-triggered D Flip-Flop is used for sampling input data 𝐷${}_{\text{in}}$ using clock 𝐶𝐾. The XOR gate outputs 3.3 volts for logic HIGH and 0 volts for logic LOW levels. The data bit and clock periods are equal and the value of Δ𝑇/𝑇${}_{\text{CK}}$ = 0.15, where the parameters Δ𝑇 and 𝑇${}_{\text{CK}}$ are shown in the figure. Assume that the Flip-Flop and the XOR gate are ideal.



If the probability of input data bit (𝐷${}_{\text{in}}$) transition in each clock period is 0.3, the average

value (in volts, accurate to two decimal places) of the voltage at node 𝑋, is _______.

The figure below shows a multiplexer where S₁ and S₀ are the select lines, I₀ to I₃ are the input data lines, EN is the enable line, and F(P, Q, R) is the output. F is

The state transition diagram for the circuit shown is